In the last years, the techniques for pirating secured integrated circuits have significantly evolved. Nowadays, the more advanced pirating techniques comprise injecting errors into determined points of an integrated circuit during the execution of so-called sensitive operations, for example authentication operations or operations of execution of an encryption algorithm. Such attacks by error injection, also called attacks by fault injection, make it possible, in combination with mathematical models, to deduce the structure of a wired-logic encryption algorithm and/or the secret keys it uses. Error injection can be made in various ways, by introducing glitches in the supply voltage of the integrated circuit, by introducing glitches in the clock signal of the integrated circuit, by exposing the integrated circuit to radiations or a laser beam, etc.
The memories present in these integrated circuits are particularly subject to this type of attack, since they contain confidential data (e.g., secret keys, passwords . . . ) that the defrauder tries to obtain.
A known method to detect an integrity defect in a memory, that is the presence of not valid data, is to verify the content of a memory, for example at the start of the integrated circuit or when read or write accessing the memory. However, such verifications cannot lead to the detection of the attacks that do not change the memory content and that only lead the memory to read data which are not those meant to be read.
This type of attack will be better understood by referring to FIG. 1, which shows a memory 1 comprising memory cells MC arranged in a memory array MA and linked to at least one address decoder ADEC by control lines CTLi. The decoder ADEC applies to the control lines CTLi memory cells selection signals Si which depend on an address ADi applied to the memory.
When an error aiming at altering data reading is injected in the memory, the error injected generally aims at the address decoder and causes a dysfunction of the same which affects the selection signals Si, so that the selected memory cells and the data read out of the memory array are not those corresponding to the address ADi.
U.S. Pat. Nos. 3,049,692 and 4,912,710 disclose a memory comprising an address decoder providing selection signals of memory cells from an address, and an encoder reconstructing an address from the selection signals applied to the memory cells. The original address and the reconstructed address are compared. In U.S. Pat. No. 3,049,692, the address is reconstructed from the memory cell selection signals using magnetic cores.